Anyone using the LJ12 full emulator and seeing odd behavior on Port D?

Anyone using the LJ12 full emulator and seeing odd behavior on Port D?

Post by no spa » Fri, 18 Jun 2004 01:49:42


I have a couple of problems-

1) An intermittent one- mysterious glitches on Port D (going from rail to
rail) output feeding the clock input on NVRAM- NVRAM seeing the glitches as
extra clocks and not responding properly. DDRD is never altered. Inspection
of the assembly code shows nothing unusual. Able to make problem happen
with BSET x,x and BCLR x,x running in an infinite loop-nothing complex
happening. Running the EM board using the PLL and multiplying the 32.768khz
up to 4.91MHZ clock. Fbus is 4*4.91Mhz. Using oscillator in emulator.

2) One port D input pin is not being read correctly- Can it be that the
emulator has a lower Vil, max than a LJ12 processor? (My signal is 0.6 v,
and the spec for a 5V processor is 1.5 V for Vil,max)