[Newbie] 64-point complex FFT with 32 bit floating-point representation

[Newbie] 64-point complex FFT with 32 bit floating-point representation

Hi all.

I'm currently trying to understand whether or not it is possible to
implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA.
As far as I understand, the critical part of the project is the
64-point complex FFT with 32 bit floating-point representation (each
real or complex number is represented in 32-bit floating-point). The
FFT block should perform this calculation in no more than 2.5 us.
I'm not an expert in this field, can anyone help me to understand
whether or not this performance is achievable with the FPGAs currently
available on the market? If yes: can you address me to some specific
FPGA model? If not: what is the critical part of my specifications? (I
suppose the time delay and the floating point spec).

This is only one of my current doubts.
I hope we can start a profitable discussion. :-)

Ciao,
Franco

[Newbie] 64-point complex FFT with 32 bit floating-point representation

Yes it is possible, you need to choose an FPGA large enough.

The FFT is relatively easy, using fixed-point arithmetic. No reason to
use floating point. Other parts of the system are more challenging.

Easily achievable without requiring a high clock rate.

The first thing you need to do is come up with an outline design for the
complete implementation, not just the FFT. Then estimate the size of
each block, and the total size of the design. Do this before you select
the FPGA, and work out what clock rate is required and how much memory
you need.

You can break each part of the design into small blocks and learn as you
go. Start with the FFT if you want, but it will not be the most
difficult part. There are many papers on different FFT architectures,
google for 'r2sdf fft' for examples.

[Newbie] 64-point complex FFT with 32 bit floating-point representation

"Franco Tiratore" < XXXX@XXXXX.COM > ha scritto nel messaggio

We have developed an 802.11b baseband and MAC in an FPGA, and
we are trying to implement an 802.11g/a baseband processor as well.
The FFT module is one of the most simplest part of the design and can
be accomodated even in a small size FPGA. But you have to implement
it using fixed point! Floating point will be an overkill...
Other parts are far more challenging to implement then the simple FFT
module, and much more resources-consuming!

If you want, you can drop me an email (for replying remov the "h"

Regards,
Antonio

[Newbie] 64-point complex FFT with 32 bit floating-point representation

Pretty much any of the current FPGA offerings are capable of 64 point
FFTs in 2.5 us. For OFDM, there really isn't any need to use floating
point. Floating point trades accuracy for dynamic range. In the case
of OFDM, you have 64 point FFT, so at most you'll have a growth of 6
bits in your data. Presumably, the data is coming from a DAC through
some filters, so the dynamic range of the data coming into the FFT is
also not that large. A single precision floating point FFt is going to
have a 24 bit data path plus an 8 bit exponent. A 24 bit fixed point
data path with no exponents is more than enough for this application.

There are FFT cores in the cores offered by the major FPGA vendors.
These are not bad considering the price (free). You can obtain
considerably higher performance and smaller size from third party IP
providers, but it is not free.

In any event, you need to look at the entire OFDM receiver, as the FFT
is only one block of it, and can be readily found off-the-shelf.