Synplify prepending Z's to top level signal names in Verilog

Synplify prepending Z's to top level signal names in Verilog

Post by jacob.bowe » Fri, 30 Jun 2006 04:01:39


Hi,

Does anyone know of a way to stop Synplify from pre-pending a "Z" to
names of top-level entity I/O signals which begin with an underscore
("_") when generating EDIF?

Thanks.
- Jacob
 
 
 

Synplify prepending Z's to top level signal names in Verilog

Post by John_ » Fri, 30 Jun 2006 05:19:55

I tried a few workaround possibilities with no joy. It looks like you're
stuck with the Z (or z). \Literals, no. Attribute syn_keep, no. Attribute
syn_edif_scalar_format in three flavors, no. IBUF instantiated, no.

Sounds like it's time for an enhancement request! I'd love to know if there
*was* a workaround outside of filtering the edif.

 
 
 

Synplify prepending Z's to top level signal names in Verilog

Post by jacob.bowe » Fri, 30 Jun 2006 07:15:34

Oh well, I guess I'm at the mercy of Synplicity and/or my perl skills.

Thanks for trying though,
- Jacob
 
 
 

Synplify prepending Z's to top level signal names in Verilog

Post by Arnau » Sat, 01 Jul 2006 03:47:54

I've had the same error too, it comes when you have specifyed false
path constraints on some of your IO signals.

If using Synplify Pro with the ucf constraint file, a workaround is to
use the output ndf file as the input constraint file to the PnR tool.
Indeed, the signals <signal> renamed <signalz> in the netlist are also
renamed <signalz> in the ndf file. The modifyed names are then
transparent to the PnR tool (at least in Xilinx ngdbuild, map and par).

Personnally I have written a small sed script which changes back the
names in the netlist.

Hopes this helps.