I am dealing with the back-annotated SDF timing simulation. The
timing_vhdl file is generated by the Xilinx ISE tool and I applied it
to the Modelsim simulator. But how can I obtain my original
input/output signal? With older tools, I can identify, for instance,
..._D is the input of Data FF, ..._Q is the output of Data FF. But now
I cannot trace these signals any more. It is dissappeard. How can I
work around this problem? Which abbreviate is short for input or
output of data flip-flop? I would appreciate any idea and suggestions.