Call for participation: SMART'10 - 4th Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion

Call for participation: SMART'10 - 4th Workshop on Statistical and Machine learning approaches to ARchitecture and compilaTion

Post by Grigori Fu » Wed, 06 Jan 2010 00:39:21


pologies if you receive multiple copies of this call.

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CALL FOR PARTICIPATION

4th Workshop on
Statistical and Machine learning
approaches
to ARchitecture and compilaTion
(SMART'10)

http://ctuning.org/workshop-smart10

January 24, 2010, Pisa, Italy

Keynote speaker: Prof. Keith Cooper
Rice University, USA

(co-located with HiPEAC 2010 Conference)
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EARLY REGISTRATION DEADLINE: JAN. 6th, 2010
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We invite you to participate in SMART'10 to be held in Pisa, Italy
on January 24, 2010, along with the conference on High-Performance
Embedded
Architectures and Compilers (HiPEAC).

The Workshop Program includes presentations of 5 selected papers
and a keynote talk by Prof. Keith Cooper, Rice University, USA on
"Moving adaptation into industrial optimizations".

The Workshop Program is now available on-line at:
http://cTuning.org/wiki/index.php/Dissemination:Workshops:SMART10:Program
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The rapid rate of architectural change and the large diversity of
architecture features has made it increasingly difficult for compiler
writers to keep pace with microprocessor evolution. This problem has
been
compounded by the introduction of multicores. Thus, compiler writers
have an
intractably complex problem to solve. A similar situation arises in
processor design where new approaches are needed to help computer
architects
make the best use of new underlying technologies and to design systems
well
adapted to future application domains.

Recent studies have shown the great potential of statistical machine
learning and search strategies for compilation and machine design. The
purpose of this workshop is to help consolidate and advance the state
of the
art in this emerging area of research. The workshop is a forum for the
presentation of recent developments in compiler techniques and machine
design methodologies based on space exploration and statistical
machine
learning approaches with the objective of improving performance,
parallelism, scalability, and adaptability.

Topics of interest include (but are not limited to):

Machine Learning, Statistical Approaches, or Search applied to

* Empirical Automatic Performance Tuning
* Iterative Feedback-Directed Compilation
* Self-tuning Programs, Libraries and Language Extensions
* Dynamic Optimization/Split Compilation/Adaptive Execution
* Adaptive Parallelization
* Low-power Optimizations
* Adaptive Virtualization
* Performance Modeling
* Performance Portability
* Adaptive Processor and System Architecture
* Architecture Simulation and Design Space Exploration
* Collective Optimization
* Self-tuning Computing Systems
* Other Topics relevant to Intelligent and Adaptive Compilers/
Architectures/OS

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Program Chair:
David Whalley, Florida State University, USA

Organizers:
Grigori Fursin, INRIA, France
John