I want to get "actual clock frequency" of my design (in ISE tool).
Due to following problem, I am having trouble.
I implemented 20-port "crossbar network" module, in which number of I/
O pins is greater than number of FPGA I/O pins.
I synthesized and got 'estimated' clock frequency.
My goal is to "place and route" my design.
What I did was to " Put dummy module to each crossbar port "
Task of these dummy modules is
- Get signals from the crossbar network
- Register (or simple dummy arithmetic functions)
- Forward the registered signals to the crossbar network.
In this way, I have only "clock, reset, result" pins in my TOP module.
Problem was that
Synthesizer optimizes, such that my dummy modules are 'almost' trimmed
Accordingly, part of my crossbar network module is also removed.
It is very time-consuming to manually modify 20 dummy modules.
Question is that
- Can we make these dummy modules 'locked' in VHDL description, so
that the synthesizer will not try to optimize?
- Is there any other way to place/route my design, when number of I/O
pins is greater than number of FPGA pins?
Thank you for comment again.