[Encounter] VHDL import possible?

[Encounter] VHDL import possible?

Post by Pasacc » Thu, 07 Feb 2008 00:17:19


For the first time, when I try to use SOC_Encounter_GXL_6.2 tool,
the synthesized VHDL netlist can not be imported.

Is it possible to import and layout the VHDL files?

Thank you in advance

1. VHDL-2002 vs VHDL-93 vs VHDL-87?

2. Module LOCK possible in VHDL?


I want to get "actual clock frequency" of my design (in ISE tool).

Due to following problem, I am having trouble.

I implemented 20-port "crossbar network" module, in which number of I/
O pins is greater than number of FPGA I/O pins.

I synthesized and got 'estimated' clock frequency.

My goal is to "place and route" my design.

What I did was to " Put dummy module to each crossbar port "

Task of these dummy modules is
- Get signals from the crossbar network
- Register (or simple dummy arithmetic functions)
- Forward the registered signals to the crossbar network.

In this way, I have only "clock, reset, result" pins in my TOP module.

Problem was that

Synthesizer optimizes, such that my dummy modules are 'almost' trimmed

Accordingly, part of my crossbar network module is also removed.

It is very time-consuming to manually modify 20 dummy modules.

Question is that

- Can we make these dummy modules 'locked' in VHDL description, so
that the synthesizer will not try to optimize?

- Is there any other way to place/route my design, when number of I/O
pins is greater than number of FPGA pins?

Thank you for comment again.

3. Is it possible to infer double data rate registers from VHDL code?

4. Is it possible to write functions in VHDL with implicit parameters?

5. Is it possible to debug a vhdl design over jtag?

6. VHDL style and possible problems for first time user

7. Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5

8. Is it possible to run Verilog and VHDL combined

9. VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions

10. HDL Node - How to import existing VHDL code

11. [VHDL] Spam on comp.lang.vhdl

12. VHDL Standards Overview of Accellera VHDL 2006 Standard 3.0

13. Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments

14. How to import a netlist in VHDL

15. Importing Structural VHDL into Cadence 4.4.6