I am trying to create a global net in the 'analog design environment'
or in the virtuoso schematic editor. I would like to create a global
net called _net0
The only global net symbols I find in analogLib or basic are for
vdd-like, vss-like or gnd-like nets. I do not find a symbol that allows
me to choose my own name.
In the analog design environment I did not succeed in specifying global
nets. There does not seem to be a place to do it.
The only work around I have now is in ADE to create the netlist ->
manually edit the input.scs -> do Simulation -> Run in ADE. I also
tried to change in the netlistHeader in the netlist directory. However,
that gets overwritten everytime a schematic is created. It does have a
"global 0" statement though.
This problem originates from simulating an extracted netlist. The
substrate node is extracted as _net0 . At this point changing the
extraction is not an option.