What's the common utilization ratio in Silicon Ensemble P&R in practice for a mid-large design?

What's the common utilization ratio in Silicon Ensemble P&R in practice for a mid-large design?

Post by walal » Wed, 08 Oct 2003 11:09:31


"Han Speek" <"Han.Speek"@ XXXX@XXXXX.COM > wrote in message
news:3f811fbc$0$260$ XXXX@XXXXX.COM ...
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Dear Han Speek,

Your comments and suggestions were of the greatest help to me. I was doing
this work blindly in the whole past month. P&R over and over and again and
again, doing trial and error... After getting your suggestions, I thought
my procedure again and again. And did a few experiments. After all, it
turned out that simply changing the "flip" and "abut" combinations matters a
lot, not to say the other factors you've mentioned about.

Now I am doing experiments on different combinations, and found out that
with 40% utilization, and "flip" + "abut" + row spacing = 1 track, I can
remove all violations! How happy I was... for the first time in this one
month, I saw violations removed for about 40% utilizations. I have seen the
violations dropped from 100000+ down to 0 magically! Thank you so much and
now I think I can do more! At the beginning of this month I was so
inexperienced that I asked too much for the SE and it got a lot of 100000+
violations after several days running...

Yet just one small problem, I still have 1 open remained after CONNECT RING
command, before I do WROUTE. Is there any search and repair kind of function
for CONNECT RING? What can I do to eliminate this only remaining OPEN? Is it
helpful to put a stripe?(Currently I am not doing any stripe, after seeing
your suggestions). Is there a incremental/search-repair "PLACE", maybe redo
"PLACE" will help?

I am a little sure that if I put "filler cells", maybe this 1 open will
gone. But I don't want to put "filler cells" because since the circuit is
large, there are a lot filler cells to add, and the post processing, for
example the layout extraction and LVS will be untolerably long... Since I am
not really doing a chip, all I need is just post-layout-extraction
transistor level simulation, so I can leave out filler cell, ...

Thank you SO MUCH for your help and now I am a lot confident about myself!
Originally I really think I am an idiot...

Best,

-Walala