Post by vlsijoth » Tue, 21 Jun 2005 19:03:56

hi all,

i have doubt in floorplanning the design in ASIC

1. when we go for flattened floorplanning or hierarchical
floorplanning.what is the adv and disadv of each of this?

2. what is the adv and disadv of hardmacro and softmacro?

3. A design is floorplanned with hard macro,my question is
whether chip area is more for floorplaning with hard macro
then the floorplanning with standard cells only(without
using hard macros). which is best? what is the adv and
disadv of each of this?

thanks in advance,
jothi murugan.B

1. Interactive floorplan

2. Questions about Timing closure Floorplan and individual timing constraints

Hi everyone:

Is there any manual about the symbols in Timing closure Floorplan, Quartu
II? I do not find a detailed description about that.

Especially, I don't clearly understand the clock control block in th
Timing closure Floorplan (Cyclone II). There is symbol calle
"...@CLKDELAYCTRL_GO". Does that mean the user can add a delay to a cloc
signal before it drives the global clock network? If this is true, how ca
I fulfill this by the setting the Quartus II?

Also,I have a question about the timing assignments for individual paths.

In the box of Assignment Name (Assigment editor window with the categor
of timing), there are two terms called" input maximum delay" and "tsu".
do not know the difference between their functions. Can this two term
have the relationship of: tsu= tclk-input maximum delay?
Or can a function implemented by " input maximum delay" be implemented b

Thank you.


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