I have two questions about CTPKS. I hope someone can answer them:
1) Divided clock: I have a programmable clock divider and I can use
the set_attribute ... ct_no_leaf "true Q" to put the generator flop
into the tree and this is handled nicely (the generator flop gets a
clock earlier in than other leaves so high speed clock to generated
clock setup/hold is ok) but the flops which are used in the clock
divider logic are connected as leaves and this causes a problem
between the flop with the clock output and the divider logic flops.
How do I tell CTPKS to move the divider logic flops (which are only
driving the clock output flop) in the tree to the same location as the
generator flop ?
2) Manual useful skew: I have some IO flops which I want to move back
in the clock tree manually. I have a buffer which drives the clock
input of these flops and during synthesis, I put a clock_tree root
constraint on it and a negative insertion delay to get what I want but
how do I tell CTPKS to connect these IO flops to an point earlier in
the clock tree than the other leaf registers ? Currently I am doing
this manually after CTPKS.
thanks for any and all help.