64-point complex FFT with 32 bit floating-point representation

64-point complex FFT with 32 bit floating-point representation

Post by Franco Tir » Fri, 12 May 2006 01:24:42


Hi all.

I'm posting here because I'm getting no response from the guys of
comp.arch.fpga
Maybe this group is more appropriate for some of my questions.

I'm currently trying to understand whether or not it is possible to
implement a 802.11a-compliant OFDM modulator/demodulator on an FPGA.
As far as I understand, the critical part of the project is the
64-point complex FFT with 32 bit floating-point representation (each
real or complex number is represented in 32-bit floating-point).
(Do you agree that this is the most critical part? And what about the
Viterbi decoder?).
The FFT block should perform this calculation in no more than 2.5 us.
I'm not an expert in this field, can anyone help me to understand
whether or not this performance is achievable with the FPGAs currently
available on the market? If yes: can you address me to some specific
FPGA model? If not: what is the critical part of my specifications? (I
suppose the time delay and the floating point spec).
Another question: how can I study the effect of reducing the number of
bits of the floating-point numbers on the trasmitted signal?

These are only some of my current doubts.
I hope we can start a profitable discussion. :-)

Ciao,
Franco
 
 
 

64-point complex FFT with 32 bit floating-point representation

Post by Ando » Fri, 12 May 2006 17:20:23


...

I can't help you out with either FPGAs or OFDM.

But a 64-point complex 32bit floating-point FFT can be executed on a
600 MHZ TigerSHARC TS-201 in about 0.96 us. Perhaps such a DSP is a
viable choice for your project (complex floating-point FFT and Viterbi
decoder are standard library routines, so development time should be at
a minimum).

FWIW,
Andor

 
 
 

64-point complex FFT with 32 bit floating-point representation

Post by Franco Tir » Fri, 12 May 2006 21:37:41

Hi, Andor!


Andor ha scritto:


Really good to know...
Is this a state-of-the-art dsp?

Ciao,
Franco
 
 
 

64-point complex FFT with 32 bit floating-point representation

Post by Ando » Fri, 12 May 2006 21:46:30


Yes - high clock rate, wide bus and VLIW. To see how the TS-201
compares with other current DSPs, check out:
http://www.yqcomputer.com/

For info on how DSP compares with FPGA:
http://www.yqcomputer.com/

Regards,
Andor
 
 
 

64-point complex FFT with 32 bit floating-point representation

Post by Franco Tir » Fri, 12 May 2006 22:10:08


Andor ha scritto:


Thanks again, Andor.
According to the guys of comp.arch.fpga, on an FPGA for OFDM in 802.11a
I have to implement a fixed-point FFT. Then the FFT is not a problem at
all.

Ciao,
Franco
 
 
 

64-point complex FFT with 32 bit floating-point representation

Post by Ray Andrak » Fri, 16 Jun 2006 10:46:45


Well, you don't HAVE to implement it in fixed point. You can do it in
floating point on an FPGA, but it really isn't necessary for OFDM and
adds considerable complexity. FWIW, I've developed a
floating point FFT for virtex4 that does ieee single precision floating
point FFTs at 400 MSamples/sec complex continuous data. That's 160ns
for a 64 point FFT. Latency through the pipeline for a fixed size 64
point transform is about 400 (1us) clocks input to output including the
reordering to present data at both ends in natural order.