RISC vs CISC Intel 8086 opcodes

RISC vs CISC Intel 8086 opcodes

Post by B'ichel » Wed, 05 Sep 2007 00:01:40



Just a quick question. of the Major processors used in Home PCs from
the 4004, 8008, 8080,8086 (I doubt this one), 6502, 6510 and 6809
which chip is the closes to RISC? I know what Risc stands for "Reduced
Instruction Set Code" but from the practical standpoint what defines a
Risc chip? The 6502 had less than 200 instructions (thats from memory
and I could be wrong), the 6809 had about 1064 of them in total. and
given what I am reading of the 8086, its loaded to the gills with
instructions.
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by no.spa » Wed, 05 Sep 2007 02:02:44

On Mon, 3 Sep 2007 15:01:40 GMT, B'ichela < XXXX@XXXXX.COM >





4004 never made it as PC cpu way to small (4bit data path).

8008 start of teh revolution at 8bits but still limited. NOT RISC.

8080,8086 (I doubt this one) NOT RISC by any stretch.


, 6502, 6510 CLOSE, May even qualify.

6809 NOT close , very CISC.
Same for 8085, Z80 Ti9900 and a much more.


Also usualy implies reduced instruction set cycle count too.
If it were only instructions 1802 would qualify but the 8/16/24 clock
cycles to execute instructions does not fit.


Total number of instructions is not a definate criteria. USually RISC
designs were more biased by simple archetectures that were very fast
(for there time) that executed simple instructions in or or two clock
cycles max. SPARC, ARM are RISC examples and 8086, 6809, 68000,
PSP11 and VAX are examples of CISC.

However ponder PDP-8, small instruction set, the real machines
(not the CMOS equivilents) executed instructions in very few cycles.

None of the machines that run CP/M or any varient is RISC.

Allison

 
 
 

RISC vs CISC Intel 8086 opcodes

Post by David Give » Wed, 05 Sep 2007 03:13:55


[...]

OTOH the PowerPC, which is marketed as RISC, has about 300 instructions, more
than the uncontroversially CISC 8080 and 6502; and while the 68000 is CISC,
the Coldfire, which uses *exactly the same instruction set* [1], is RISC!

These days I reckon that modern processor design has taken on board the good
features of both the classic RISC *and* CISC designs, and as a result the
terms don't mean much any more.



[1] Okay, okay, not quite exactly. The Coldfire actually uses a subset of the
68000 opcodes. However, it's such a large subset that people have been
building binary-compatible Amiga clones using Coldfire processors. I have no
idea how *anyone* can consider these things RISC.

--
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"There does not now, nor will there ever, exist a programming language in
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RISC vs CISC Intel 8086 opcodes

Post by Thierry B » Wed, 05 Sep 2007 04:32:58

--{ B'ichela a plopceci: }--
>> Risc chip? The 6502 had less than 200 instructions (thats from memory >> and I could be wrong), the 6809 had about 1064 of them in total. and >> given what I am reading of the 8086, its loaded to the gills with >> instructions.

If my memory wasn't corrupted by cosmic rays, first ARM chips
have only 27 instructions...

--
"Le mecin, depuis qu'il a l'ordinateur, quand il te parle, il te
regarde plus : il regarde son ordinateur avec une tronche, mon pauvre,
on dirait qu'il a bouffun ver."
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by glen herrm » Wed, 05 Sep 2007 06:34:09


Among others are fixed size, or a small number sizes of instructions,
and simple addressing modes. Usually a load/store architecture.
That is, load and store to memory, all operations are between
registers.


Are you including different addressing modes in the instruction count?

There was a trend for a while in making more complex instructions
to simplify life for assembly programmers. When it was found that
compilers didn't need those, the RISC idea was formed.

-- glen
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by no.spa » Wed, 05 Sep 2007 07:39:26

On Mon, 03 Sep 2007 19:13:55 +0100, David Given < XXXX@XXXXX.COM >




A large instruction set is usually a function of instruction word
size.


I'd argue that the one instuction per clock cycle is a significant
part of the criteria.


Likely because of the small number of clock cycles needed to execute
an instruction compared to any varient of the 68k.

In it's heyday of usage RISC and MIPS(millions of instructions per
second) usually were associated with raw speed.

How about DEC Alpha wich is supposedly RISC but can run soft emulation
code to run VAX a notably CISC machine?

After the mid 90s between sophisticated compilers and increasingly
sophisticated archetectures the distincion of RISC still stands
against noticeably CISC machines.

For me processors like 6502 were near RISC and proved simple and
moderatly fast is viable against complex of the same general computing
speed. What drove RISC in the 80s was for a given silicon
foundary capability a die could have only so many transistors and
with that upper limit complexity or speed was the trade. So the ARM,
SPARC and other similar designs were cheap to build silicon, fast and
for the number of transistors on the die small.

As to reduced instruction sets, I still hold the PDP8 cut it to the
bone and still proved to be effective. In it's day it was trying to
reduce the amount of logic (transistors!) required to make a viable
machine. Nearly 20years later the proces repeats itself as how
many transistors on a die.


Allison
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by glen herrm » Wed, 05 Sep 2007 09:33:45

XXXX@XXXXX.COM wrote:

(snip)


Instruction count isn't a very good measure. You could be CISC with
a very small number of instructions and a large number of instruction
modifiers.

I would say that the 6502 and 8080 should be in a different class
altogether. CISC uses a lot of logic, often with microcode, to
implement complex operations. (Even floating point was pretty
complex for a 360/40.) RISC uses a lot of transistors to do simple
operations fast, often with many registers. For the 8080 and 6502,
I would say the goal wasn't fast, but to do useful operations at all.

One I still remember is that the 6502 CALL doesn't store the address
of the next instruction, but one byte earlier.




I agree, though I don't know that it was the right way. That included
leaving multiply and divide out of early processors (and not so early
ones) because they couldn't be done in one cycle.




MIPS - Meaningless Indicator of Processor Speed.


That doesn't seem quite fair. Any good machine can emulate most
other machines. Alpha does have an advantage in hardware
support for VAX floating point formats, though.



I would say that even the 6502 has too many address modes, and
too variable instruction length, but definitely is low in transistors.

For RISC, I see the goal not as low transistors but the most
processing for a given number of transistors. RISC is often
register rich. The CDP1802 would probably be the most RISC-like
of the early generation microprocessors.


I agree, the PDP-8 does seem RISC like.

In one of Knuth's books there is discussion of a two instruction
machine.

-- glen

 
 
 

RISC vs CISC Intel 8086 opcodes

Post by Roger Ivi » Wed, 05 Sep 2007 11:30:47


Much as I love the sleek, simple, PDP-8 instruction set, have you folks
considered all the work that has to go on for something like
JSR I Z 10?

- Fetch instruction
- Fetch Z 10
- Write incremented Z 10
- Write return address

Not exactly the RISC ideal. When I though about it a few years ago, it
looked to me like you'd need five-ported memory to execute a PDP-8
instruction in one cycle. But then, I might have been fiddling with the
PDP-5, which stores the PC at location 0...


If you spend some time with Google, you can find some folks who have
played with a single instruction: subtract and branch on borrow.

Another scheme I've seen involved a single instruction that moved a word
in a byte-addressed machine. Addition was performed by constructing
suitable tables. Branches were done by making the PC addressable. Most
practical MOVE machines that I've seen discussed (like the British DEUCE
of the '50s) simply moved the opcode into the address space, so I'm not
really certain they count.
--
roger ivie
XXXX@XXXXX.COM
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by David Give » Wed, 05 Sep 2007 17:49:38


[...]

Yeah, OISC machines. While they can be implemented with an impressively small
number of transistors, the memory bandwidth is prohibitive; each 'instruction'
consists of three words (source address, address of value to subtract, address
to jump to on borrow) and the 'instructions' are so primitive that you need to
churn your way through lots of them to achieve anything.


Indeed. I designed an ISA like this once when I was feeling bored; it exposed
all the internal devices, and each 'instruction' consisted of
pick-up-value-at-this-internal-address, write-to-that-internal-address. It
allowed a number of interesting features, like multiple ALUs and memory access
devices; but it was extremely interesting that when I tried hand-rolling some
code for it, the code density was extremely similar to that of traditional
processors...

http://www.yqcomputer.com/

Now all I need to do is to learn enough VHDL to implement one. (Or, more
likely, discover out why it wouldn't work.)

--
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"There does not now, nor will there ever, exist a programming language in
which it is the least bit hard to write bad programs." --- Flon's Axiom
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by B'ichel » Thu, 06 Sep 2007 08:34:29


In the case of the 6809 I was. not because I was trying to be
a fool but because the number of instructions/variation of
instructions stuck in my head at over 1,464. I don't remember how manh
the 6502 and its kin had.
Given now that the computer compiles programs written in high
level languages, the neat shortcuts are not as often used. but... Do
these shortcut instructions really save time in program execution vs
a compiled program written in C or Pascal? Certainly a compiler could
make use of the shortcuts if the compiler could be designed to use the
shortcuts effectivly.

--

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Web Site: http://www.yqcomputer.com/ , Dialup 860-618-3091 300-33600 bps
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B'ichela
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by glen herrm » Thu, 06 Sep 2007 10:34:14


(snip)


I could crosspost to comp.compilers, but...

It is easy to use a dynamic programming algorithm in a compiler to
select the optimal instruction sequence if you can put a cost to each
instruction or instruction group. What is easy for a compiler may not
be so easy for a person, and vice versa.

Also, when memory was more expensive there was more need for
compact instructions sets, another advantage for CISC.
VAX is said to have been designed to reduce code size at the
expense of complex instructions. Some examples are a bounds
check instruction for array access and POLY to evaluate a
polynomial. On some processors those were slower than doing
the operation using separate instructions!

-- glen
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by pete » Thu, 06 Sep 2007 13:58:00

In article < XXXX@XXXXX.COM >
XXXX@XXXXX.COM "B'ichela" writes:



It's years since I worked with a 6502 but seem to recall there
were only around 40 or 50 instructions. The 6811 I worked on
more recently had a few more for the additional accumulator, but
the total must have been still firmly in double figures. And
this latter's instruction set is wonderfully orthogonal.

Pete
--
"We have not inherited the earth from our ancestors,
we have borrowed it from our descendants."
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by David Give » Fri, 07 Sep 2007 04:19:26


[...]

Here's an interesting comment I found in the 68000 code generator for the ACK:

/* #define FANCY_MODES 1
/* On the M68020, there are some real fancy addressing modes.
Their use makes the code a bit shorter, but also much slower.
The FANCY_MODES #define enables the use of these addressing
modes.
*/

So that author obviously thought not.

--
€ €€€ http://www.yqcomputer.com/ €€€€€€€€€€€€€€€€€€€
"There does not now, nor will there ever, exist a programming language in
which it is the least bit hard to write bad programs." --- Flon's Axiom
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by dkelve » Sun, 16 Sep 2007 01:56:37


---snip---
Hi
I thought I'd add a little here. Current day x86 processors use RISC
engines
internally. Transmeta even took x86 instructions and created RISC
instructions
externally.
With a wide memory bandwidth, such as many minis and main frames had
in
the past, RISC makes a lot of sense. It has been shown to be most
effective
at getting things done.
This makes sense for a $100K machine. It doesn't make sense for a
$1.5K
machine. In order to make better use of memory bandwidth, the
compaction
of CISC like instructions makes better sense. Once in the processor,
these
can be expanded to RISC like operation in an internal cache.
As we move into the future, we'll see the memory bottle neck issue
even
move into the larger machines.
I'm not saying that the x86 set is the best useage of memory
bandwidth
but it is better than most RISC instruction sets.
A next generation processor would have to consider that effective use
of memory bandwidth is much more important than compiler simplicity.
More complicated CISC processors will continue to move ahead of
external RISC machines, even though the internal engine might still be
RISC in nature.
This is a simple problem of the speed increase of internal processing
exceding the speed of wires.
Dwight
 
 
 

RISC vs CISC Intel 8086 opcodes

Post by David Give » Sun, 16 Sep 2007 03:45:18


[...]

Actually, the IA32 architecture is known for having lousy code density --- ARM
is better than it, and ARM Thumb is better than ARM, and the M-Core (a
Motorola Thumb rip-off) is even better than Thumb. All three processors are
about as RISC as they get.

(Comparing identical builds of gcc's cc1 internal executable, the ARM version
has a code segment size of 0x0037857c; the IA32 version is 0x0041c0d8.
Unfortunately I don't have a Thumb or M-Core version handy, but Thumb
typically gains 30% over ARM.)

It's interesting that one of the least code dense RISC processors is the
PowerPC --- which also has one of the least RISC instruction sets around...

--
€ €€€ http://www.yqcomputer.com/ €€€€€€€€€€€€€€€€€€€
"There does not now, nor will there ever, exist a programming language in
which it is the least bit hard to write bad programs." --- Flon's Axiom