FIG. 4A shows the connections between the IDE interface 86, the MCA to
IDE BIC 70, the data buffers 72, the MICRO CHANNEL bus 66, and certain
miscellaneous discrete components. In addition to data and address
lines, eight of the well-known IDE interface lines must be
generated/manipulated to interface an IDE drive to the MICRO CHANNEL
bus: CS1FX--, CS3FX--, DIOR--, DIOW--, IOCS16--, IORDY, INTRQ, and
RESET--, where the "--" indicates an active low signal. The MCA to IDE
BIC 70 manipulates certain MICRO CHANNEL bus lines, as shown in FIGS. 4A
and 4B, to generate the above eight IDE interface lines.
The IDE interface 86 connects to the system planar 20 via connector J1.
Connector J1 is a 2 by 20 BERG connector, as is well known in the art.
The other circuitry 99 shown in FIG. 4B corresponds to the remaining
circuitry of the MCA to IDE BIC 70. The lines connecting to the other
circuitry 99, as labeled in FIGS. 4A and 4B, correspond to the lines and
labels used in FIGS. 5A to 5I, which show the remaining internal details
of the MCA to IDE BIC 70.
The data bus of the MICRO CHANNEL bus is interfaced to the IDE data bus
via two 74ALS245 bidirectional buffers 72. The data buffers 72 comprise
two 74ALS245 buffers 72a and 72b, which are well known in the art and
are electrically connected as shown in FIG. 4A to connector J1, the MCA
to IDE BIC 70, and the MICRO CHANNEL bus 66.
The discrete components-inductor L1, resistors R1, R2, & R3, and
capacitors C1 & C2--are all connected as shown in FIGS. 4A and 4B.
Inductor L1 is used to minimize ringing and glitches on the IDE RESET
line. Resistors R3 and R2 are 10 K? 5% 0.0833 watt pullup resistors used
to pull their respective lines up to a logical ONE. Resistor R1 is a 1
K? 5% 0.0833 watt resistor that is used to pull the IDE-- IRQ line to a
known state. These three lines are outputs from the IDE drive and inputs
to the MCA to IDE BIC 70. In certain circumstances, an IDE hardfile may
not always be connected to the system 10. As such, resistors R1-R3
ensure that the MCA to IDE BIC 70 does not receive floating signals in
the unlikely event that the hardfile is removed. Capacitors C1 and C2
are 100 pF 10% ceramic capacitors used to prevent certain EMC problems.
The MCA to IDE BIC 70 comprises the circuitry shown in FIGS. 4A and 4B
and 5A to 5I. Specifically, the MCA to IDE BIC comprises address decode
logic 100, separate level sensitive scan design (LSSD) latches 102, LSSD
latches with common clocks 104, inverters 106, simple combinatorial
logic blocks 108, complex combinatorial logic blocks 110, an LSSD latch
with ANDed inputs 112, additional separate LSSD latches 114, a tristate
inverting buffer 116, a simple multiplexer 118, several DELAYs
120a-120c, and a tristate read multiplexer 122, in electrical circuit
communication, as shown in FIGS. 4A, 4B, and 5A to 5I.
Logical inverters 106?, 106?, and 106a-106o are common logic inverters,
as are well known in the art. Simple logic blocks 108a-108hh comprise
AND, NAND, OR, NOR, and XNOR gates, as are well known in the art.
Complex logic blocks 110a-110m are self explanatory. For example,
complex logic blocks 110a and 110a are 3 OR-AND complexes, comprising
two (2) three- (3-) input OR gates, with the outputs of the OR gates
ANDed together to form the output O. Likewise, complex logic block 110h