May 1st release of FPGA Transputer

May 1st release of FPGA Transputer

Post by JJ » Wed, 04 May 2005 09:01:53

Hello all

As of last April 1st I decided to do monthly updates for those
interested in following progress on the FPGA Transputer and its V++
compiler. But I have to skip this one since I am writing up a lengthy
conference paper that I hope to give in september.

Anyway this months release which will now be for June 1st will feature
the V++ compiler in the 1st version that can generate executable
machine code for the R16 ISA simulator. These are now combined into 1
module, V++ can compile RPN for expressions and control flow nested
blocks and only minimally for the remaining part of the language (which
mixes Verilog with C and some occam).

The expression code goes through temporary register allocation to
symbolic machine code and looks good. V++ does not do the usual
optimizations for common sub expression elimination and others at that
level but does minimize generated opcodes which use prefixes.

The control flow nested RPN goes through a !&&|| short circuit branch
reduction and replaces those with minimum spanning BT BF BR codes. Also
looks good across nested statements.

These 2 parts then go through final emit stage to encode variable
length codes, this was preempted by the paper.

No special output format since the hex array of codes will be executed
by the ISA simulator.

The 3rd part of the compiler RPN is not ready for primetime since there
is little type checking, declaration, function or process code
analysis. That limits code that can be usefully compiled to effectively
complex blocks with no functions.

The idea is to get the ISA simulator busy again with some realistic
code samples rather than executing trivial #defined preprocessed hex
data. Having the V++ compiler up and ready will allow for the simulator
to explore some different options that have to be decided in laying out
machine data structures for the scheduler and stack frames.

Also I decided to take the new inverted page MMU from the cpu and add
that to the ISA simulator and a tester. The results look so good that I
removed the V++ symbol table hash code and will replace with the MMU
calls. This will give the MMU a workout that it wouldn't normally get
if just another part of the Transputer under test. This MMU features
new(), delete() and adjust() in HW down to 32byte block allocation over
any size address space small or large.

The rest of the V++ compiler will pick up again after the ISA and RTL
models have moved forward significantly or as when needed.

Back in June

johnjakson at usa dot com
transputer2 at yahoo dot com

May 1st release of FPGA Transputer

Post by DerekSimmo » Wed, 04 May 2005 14:10:51

Where can you find the current release of the FPGA Transputer project?



May 1st release of FPGA Transputer

Post by JJ » Wed, 04 May 2005 17:01:27

As ever by request although a web set up is still pending ,,

Since the current release is still the April 1 release warts and all
and that didn't include the compiler so its really just the docs as
they were then plus the ISA simulator which isn't that big anyway. The
Verilog and RTL code will stay hidden till I figure what the deal is.

It would be nice to get the paper out too when its done but I don't
think I can do that although some of it is coming from the partially
edited docs.

May 1st release of FPGA Transputer

Post by Zigg » Thu, 05 May 2005 10:14:52

Hes not ofically released his project yet, as its not 'complete'.. For
now its by request only to people that can handle the 'missing pieces'..

For the rest of us mere mortals, we sit and wait paitently for things to
solidify. :)