I've taken a quick run over to this oslink-interface. os means
oversampling. Nothing there ... and you have to do it. Sampling far
away from the middle of a bit-cell is a flaw! Please check "Data to
Clock Phase Alignment XAPP225" from Xilinx.
I have selected this approach for my pci-link-adapter and it works
still very well.
Your real challange is to handle different clockdomains and convert a
multiple continous byte stream protocol to a discontinous multibyte
block protocol with low systemimpact ;-)